1. Field of the Invention
The present invention concerns an array of electrically programmable non-volatile semiconductor memory cells comprising ROM (Read Only Memory) memory cells.
2. Discussion of the Related Art
Generally, in semiconductor devices it is often necessary to store permanently some information, that can be necessary for operating the device or for identifying the same.
This is true in particular for electrically programmable non-volatile semiconductor memory devices, such as EPROM, Flash EEPROM and EEPROM memories. In such devices said information (e.g., for identifying the device) is stored in one or more rows of EPROM, Flash EEPROM or EEPROM memory cells, respectively, belonging to the array of memory cells of the device.
However, it is known that EPROM, Flash EEPROM and EEPROM memory cells include floating-gate MOS transistors, and the information is stored by means of charge trapped in the floating gate. The information might thus be lost for several reasons, in particular due to a loss of charge by the floating gates of the memory cells.
In order to permanently store the information, ROM memory cells are to be used. Conventionally, a ROM memory cell is formed by a MOS transistor, e.g. with an N-type channel, having N-type drain and source regions formed in a P-type substrate or well and spaced apart. The portion of P-type substrate or well between the source and drain regions forms a channel region, and a gate electrode is placed above the channel region with the interposition of a thin gate oxide layer.
Programming of a ROM memory cell is made during the manufacturing thereof, either by means of dedicated process steps or by means of a structure suitable for making the cell non-conductive. This can be made, for example, by implanting a dopant in the channel region, so as to vary the threshold voltage of the cell.
The interposition of ROM memory cells in an EPROM, Flash EEPROM or EEPROM memory device for storing information that might get lost is however disadvantageous under several respects.
Firstly, it is necessary to provide, in the normal manufacturing process flow for the EPROM, Flash EEPROM or EEPROM memories, additional process steps and photolithographic masks dedicated for forming the ROM cells. This causes an increase in the manufacturing costs.
Secondly, the ROM memory cells cannot be integrated in the same array of EPROM, Flash EEPROM or EEPROM memory cells, because having a different layout they would cause irregularities. It is thus necessary to provide suitable small arrays of ROM memory cells. This however causes an increase in the overall area of the memory device, and thus an increase of the manufacturing costs.
Thirdly, addressing and sensing of the ROM cells require dedicated circuits normally different from those already provided for addressing and sensing EPROM, Flash EEPROM or EEPROM memory cells, and this has the consequence of an increase in the overall area of the memory device and in the complexity of the design.
All this makes it disadvantageous to provide, in an electrically programmable non-volatile memory device, a small array of ROM cells for permanently storing identifying information.